Method and apparatus for controlling metal doping of a chalcogenide memory element

ABSTRACT

A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a silver layer over a chalcogenide glass layer. Processing the silver layer via heat treating, light irradiation, or a combination of both to form a layer comprising silver interstitially formed in a chalcogenide glass layer; silver-selenide formed in a layer comprising silver interstitially formed in a chalcogenide glass layer; or a silver doped chalcogenide glass layer having silver-selenide formed therein.

FIELD OF THE INVENTION

[0001] The invention relates to the field of random access memory (RAM)devices formed using a resistance variable material, and in particularto controlling silver incorporation into a resistance variable memoryelement formed using chalcogenide glass.

BACKGROUND OF THE INVENTION

[0002] A well known semiconductor memory component is random accessmemory (RAM). RAM permits repeated read and write operations on memoryelements. Typically, RAM devices are volatile, in that stored data islost once the power source is disconnected or removed. Non-limitingexamples of RAM devices include dynamic random access memory (DRAM),synchronized dynamic random access memory (SDRAM) and static randomaccess memory (SRAM). In addition, DRAMS and SDRAMS also typically storedata in capacitors which require periodic refreshing to maintain thestored data.

[0003] Recently resistance variable memory elements have beeninvestigated for suitability as semi-volatile and non-volatile randomaccess memory elements. In a resistance variable memory element, aconductive material, such as silver, is incorporated into a dielectricmaterial. The resistance of the conductive material containingdielectric material can be changed between high resistance and lowresistance states. The resistance variable memory element is normally ina high resistance state when at rest. A write operation to a lowresistance state is performed by applying a voltage potential across thetwo electrodes.

[0004] One preferred resistance variable material comprises achalcogenide glass. A specific example is germanium-selenide(Ge_(x)Se_(100−x)) containing a silver (Ag) component. One method ofproviding silver to the germanium-selenide composition is to initiallyform a germanium-selenide glass and then deposit a thin layer of silverupon the glass, for example by sputtering, physical vapor deposition, orother known techniques in the art. The layer of silver is irradiated,preferably with electromagnetic energy at a wavelength less than 600nanometers, so that the energy passes through the silver and to thesilver/glass interface, to break a chalcogenide bond of the chalcogenidematerial such that the glass is doped or photodoped with silver. Anothermethod for providing silver to the glass is to provide a layer ofsilver-selenide on a germanium-selenide glass. A top electrodecomprising silver is then formed over the silver-germanium-selenideglass or in the case where a silver-selenide layer is provided over agermanium-selenide glass, the top electrode is formed over thesilver-selenide layer.

[0005] It has been found that over time devices fabricated via the abovedescribed methods fail if excess silver from a top silver containingelectrode continues to diffuse into the silver germanium-selenide glassor into the silver-selenide layer and eventually into thegermanium-selenide glass layer (the primary switching area) below thesilver-selenide layer.

[0006] Furthermore, during semiconductor processing and/or packaging ofa fabricated structure that incorporates the memory element, the elementundergoes thermal cycling or heat processing. Heat processing can resultin substantial amounts of silver migrating into the memory elementuncontrollably. Too much silver incorporated into the memory element mayresult in faster degradation, i.e., a short life, and eventually devicefailure.

[0007] Control of the amount of available silver which enters the glasswould be highly desirable to prevent premature memory cell failure.

BRIEF SUMMARY OF THE INVENTION

[0008] The present invention is a method of controlling silver doping ofa chalcogenide glass in a resistance variable memory element. The methodincludes forming a first chalcogenide glass layer; forming a firstsilver-selenide layer in contact with the first chalcogenide glasslayer; forming a second chalcogenide glass layer in contact with thefirst silver-selenide layer; forming a silver layer in contact with thesecond chalcogenide glass layer; processing the silver layer and secondchalcogenide glass layer to incorporate silver into the secondchalcogenide glass layer, thereby forming one or more silver containinglayers; and removing any remaining portions of the silver layer.Electrodes are provided in contact with the first chalcogenide layer andthe one or more silver containing layers. Forming a resistance variablememory element in accordance with the invention limits the amount ofsilver available for diffusion into the first glass layer.

[0009] The silver layer and second chalcogenide glass layer may beprocessed by heat treating, light irradiation or a combination of bothheat treating and light irradiation. Heat treating the silver layer willcause silver to be incorporated into the second chalcogenide glassinterstitially. Processing the second chalcogenide glass layer withlight irradiation will cause the formation of a silver dopedchalcogenide glass layer having silver-selenide formed therein.Combining a heat treating process with light irradiation will result insilver-selenide formed in a chalcogenide glass layer having silverinterstitially formed in the chalcogenide glass layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] These and other features and advantages of the invention will bebetter understood from the following detailed description, which isprovided in connection with the accompanying drawings.

[0011]FIG. 1 illustrates a cross-sectional view of a memory elementfabricated in accordance with a first embodiment of the invention and atan initial stage of processing.

[0012]FIG. 2 illustrates a cross-sectional view of the memory element ofFIG. 1 at a stage of processing subsequent to that shown in FIG. 1.

[0013]FIG. 3 illustrates a cross-sectional view of the memory element ofFIG. 1 at a stage of processing subsequent to that shown in FIG. 2.

[0014]FIG. 4 illustrates a cross-sectional view of the memory element ofFIG. 1 at a stage of processing subsequent to that shown in FIG. 3.

[0015]FIG. 5 illustrates a cross-sectional view of the memory element ofFIG. 1 at a stage of processing subsequent to that shown in FIG. 4.

[0016]FIG. 6 illustrates a cross-sectional view of the memory element ofFIG. 1 at a stage of processing subsequent to that shown in FIG. 5.

[0017]FIG. 7 illustrates a cross-sectional view of the memory element ofFIG. 1 at a stage of processing subsequent to that shown in FIG. 6 inaccordance with a first embodiment of the inventor.

[0018]FIG. 8A illustrates a cross-sectional view of the memory elementof FIG. 1 at a stage of processing subsequent to that shown in FIG. 6 inaccordance with a second embodiment of the inventor.

[0019]FIG. 8B illustrates a cross-sectional view of the memory elementof FIG. 1 at a stage of processing subsequent to that shown in FIG. 8Ain accordance with a second embodiment of the inventor.

[0020]FIG. 8C illustrates a cross-sectional view of the memory elementof FIG. 1 at a state of processing subsequent to that shown in FIG. 8Bin accordance with a second embodiment of the inventor.

[0021]FIG. 9 illustrates a cross-sectional view of the memory element ofFIG. 1 at a stage of processing subsequent to that shown in FIG. 6 inaccordance with a third embodiment of the inventor.

[0022]FIG. 10 illustrates a cross-sectional view of the memory elementof FIG. 1 at a stage of processing subsequent to that shown in FIG. 7.

[0023]FIG. 11 illustrates a cross-sectional view of the memory elementof FIG. 1 at a stage of processing subsequent to that shown in FIG. 10.

[0024]FIG. 12 illustrates a processor-based system having a memoryelement formed according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0025] In the following detailed description, reference is made tovarious specific embodiments of the invention. These embodiments aredescribed with sufficient detail to enable those skilled in the art topractice the invention. It is to be understood that other embodimentsmay be employed, and that various structural, logical and electricalchanges may be made without departing from the spirit or scope of theinvention.

[0026] The term “substrate” used in the following description mayinclude any supporting structure including, but not limited to, aplastic or a semiconductor substrate that has an exposed substratesurface. A semiconductor substrate should be understood to includesilicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), dopedand undoped semiconductors, epitaxial layers of silicon supported by abase semiconductor foundation, and other semiconductor structures. Whenreference is made to a semiconductor substrate or wafer in the followingdescription, previous process steps may have been utilized to formregions or junctions in or over the base semiconductor or foundation.

[0027] The term “silver” is intended to include not only elementalsilver, but silver with other trace metals or in various alloyedcombinations with other metals as known in the semiconductor industry,as long as such silver alloy is conductive, and as long as the physicaland electrical properties of the silver remain unchanged.

[0028] The term “silver-selenide” is intended to include various speciesof silver-selenide, including some species which have a slight excess ordeficit of silver, for instance, Ag₂Se, Ag_(2+x)Se, and Ag_(2−x)Se.

[0029] The term “chalcogenide glass” is intended to include glasses thatcomprise an element from group VIA (or group 16) of the periodic table.Group VIA elements, also referred to as chalcogens, include sulfur (S),selenium (Se), tellurium (Te), polonium (Po), and oxygen (O).

[0030] The invention will now be explained with reference to FIGS. 1-10,which illustrate exemplary embodiments of a resistance variable memoryelement 100 fabricated in accordance with the invention. FIG. 1 depictsa portion of an insulating layer 12 formed over a semiconductorsubstrate 10, for example, a silicon substrate. It should be understoodthat the resistance variable memory element can be formed on a varietyof substrate materials and not just semiconductor substrates such assilicon. For example, the insulating layer 12 may be formed on a plasticsubstrate. The insulating layer 12 may be formed by any known depositionmethods, such as sputtering by chemical vapor deposition (CVD), plasmaenhanced CVD (PECVD) or physical vapor deposition (PVD). The insulatinglayer 12 may be formed of a conventional insulating oxide, such assilicon oxide (SiO₂), a silicon nitride (Si₃N₄), or a low dielectricconstant material, among many others.

[0031] A first electrode 14 is next formed over the insulating layer 12,as also illustrated in FIG. 1. The first electrode 14 may comprise anyconductive material, for example, tungsten, nickel, tantalum, aluminum,or platinum, among many others. A first dielectric layer 15 is nextformed over the first electrode 14. The first dielectric layer 15 maycomprise the same or different materials as those described above withreference to the insulating layer 12.

[0032] Referring now to FIG. 2, an opening 13 extending to the firstelectrode 14 is formed in the first dielectric layer 15. The opening 13may be formed by known methods in the art, for example, by aconventional patterning and etching process. A first chalcogenide glasslayer 17 is next formed over the first dielectric layer 15, to fill inthe opening 13, as shown in FIG. 3.

[0033] The first chalcogenide glass layer 17 is preferably agermanium-selenide glass having a Ge_(x)Se_(100−x) stoichiometry. Thepreferred stoichiometric range is between about Ge₁₈Se₈₂ to aboutGe₄₃Se₅₇ and is more preferably about Ge₄₀Se₆₀. The first chalcogenideglass layer 17 preferably has a thickness from about 100 Å to about 1000Å and is more preferably between about 150 Å to about 200 Å.

[0034] The use of a metal containing layer, such as a silver-selenidelayer, in contact with the chalcogenide glass layer makes it unnecessaryto provide a metal (silver) doped chalcogenide glass, which wouldrequire photodoping of the substrate with light radiation.

[0035] The formation of the first chalcogenide glass layer 17, having astoichiometric composition in accordance with the invention may beaccomplished by any suitable method. For instance, evaporation,co-sputtering germanium and selenium in the appropriate ratios,sputtering using a germanium-selenide target having the desiredstoichiometry, or chemical vapor deposition with stoichiometric amountsof GeH₄ and SeH₂ gases (or various compositions of these gases), whichresult in a germanium-selenide film of the desired stoichiometry areexamples of methods which may be used to form the first chalcogenideglass layer 17.

[0036] Referring now to FIG. 4, a first metal containing layer 18,preferably silver-selenide, is deposited over the first chalcogenideglass layer 17. Other suitable metal containing layers 18 may includesilver-chalcogenide layers, for example, silver sulfide, silver oxide,and silver telluride. A variety of processes can be used to form themetal containing layer 18. For instance, physical vapor depositiontechniques such as evaporative deposition and sputtering may be used.Other processes such as chemical vapor deposition, co-evaporation ordepositing a layer of selenium above a layer of silver to formsilver-selenide can also be used.

[0037] The layers may be any suitable thickness and depends upon thedesired electrical switching characteristics. The thickness of thelayers is such that the metal containing layer 18 is thicker than thefirst chalcogenide glass layer 17. The metal containing layer 18 is alsothicker than a second glass layer, described below. The first metalcontaining layer 18 preferably has a thickness from about 300 Å to about600 Å.

[0038] Referring now to FIG. 5 a second chalcogenide glass layer 20 isformed over the first metal containing layer 18. The second chalcogenideglass layer 20 allows deposition of silver above the metal containinglayer 18, for example, a silver-selenide layer, since silver cannot bedirectly deposited on silver-selenide.

[0039] The second chalcogenide glass layer 20 is preferably agermanium-selenide glass having a Ge_(x)Se_(100−x) stoichiometry. Thepreferred stoichiometric range of the second glass layer depends on thetype of processing the layer will undergo, i.e., thermal, lightirradiation or a combination of thermal and light irradiation. Thesecond chalcogenide glass layer 20 preferably has a thickness betweenabout 150 Å to about 500 Å and is more preferably 200 Å.

[0040] The formation of the second chalcogenide glass layer 20 may beaccomplished by any suitable method. For instance, chemical vapordeposition, evaporation, co-sputtering, or sputtering using a targethaving the desired stoichiometry, may be used.

[0041] Referring now to FIG. 6, a silver layer 22 is formed over thesecond chalcogenide glass layer 20. The silver layer is preferablybetween about 150 Å to about 300 Å thick. The silver layer may bedeposited by any suitable mechanism, for instance, physical vapordeposition (PVD) or evaporation. Next the silver layer 22 is thermallytreated, irradiated with light, or thermally treated in combination withthe irradiation treatment to cause sufficient diffusion of silver intothe second chalcogenide glass layer 20.

[0042] Referring now to FIG. 7, the silver layer 22 and the secondchalcogenide glass layer 20 are thermally treated, preferably by heatannealing in order to form a silver-containing chalcogenide glass layer20a wherein silver is incorporated interstitially. The preferredstoichiometric range of the second chalcogenide glass layer 20 forthermal processing is between about Ge₁₈Se₈₂ to about Ge₄₃Se₅₇ and ismore preferably about Ge₄₀Se₆₀. A suitable annealing temperature is anelevated temperature close to or slightly below the thin film glasstransition temperature of the second chalcogenide glass layer 20. Theannealing temperature may be as low as 50° C. and as high as about 350°C. The preferred annealing temperature depends on the chosen glassstoichiometry. The substrate is preferably annealed for about 5 to about15 minutes and more preferably about 10 minutes. The annealingpreferably takes place in an atmosphere containing oxygen. A wet etch innitric acid is then performed to remove any remaining portion of silverlayer 22.

[0043] Referring now to FIGS. 8A-8C, alternatively silver from thesilver layer 22 may be incorporated into the second chalcogenide glasslayer 20 via irradiation with light. The silver layer 22 is irradiatedwith light to cause diffusion of silver ions from silver layer 22 intothe second chalcogenide glass layer 20 thereby forming a silver dopedchalcogenide glass layer 20 d. For example, when the second chalcogenideglass layer includes germanium-selenide, irradiation further causes theformation of regions of silver-selenide 20 e in the silver dopedchalcogenide glass layer 20 d. Research in this area is reported in thearticle “Dual Chemical Role of Ag as an Additive in ChalcogenideGlasses” by Mitkova et al., Physical Review Letters, Vol. 83, No. 19(1999), pgs. 3848-3851, the disclosure of which is incorporated hereinby reference.

[0044] The preferred stoichiometric range for light irradiationprocessing is between about Ge₁₈Se₈₂ to about Ge₃₃Se₆₇ and is morepreferably about Ge₂₅Se₇₅. Preferably, about 1% to about 10% less thanthe maximum amount of silver necessary to keep the glass layer 20 in anamorphous state is diffused into the glass layer. Any residual glass 23will preferably have a lower stoichiometry than the pre-processingsecond chalcogenide glass layer 20. Accordingly, a silver-dopedgermanium-selenide glass layer having regions of silver-selenide 20 bincorporated therein, and a layer containing any remaining undoped glass23 are formed. The silver layer 22 may be irradiated with any suitablelight, for example, visible light or ultraviolet light. The silver layer22 may be irradiated for about 5 to about 15 minutes at about 1 to about10 mw/cm² with light between 200-600 nm. Any remaining silver layer isthen removed, for example, via wet etching in nitric acid.

[0045] Not to be held to any particular theory, it is believed that asthe silver layer 22 and second chalcogenide glass layer 20 areirradiated with light over time there is an initial doping of silverinto the second chalcogenide glass layer 20 forming a structure having asilver doped chalcogenide glass layer 20d formed between the silverlayer 22 and any remaining undoped second chalcogenide glass layer 23 asshown in FIG. 8A. With further irradiation, regions ofsilver-chalcogenide, for example, silver-selenide, 20 e are formed inthe silver doped chalcogenide glass layer 20 d as show in FIG. 8B. Forpurposes of simplified discussion, silver-chalcogenide 20 e will befurther described herein as silver-selenide. However, it should beunderstood that other silver-chalcogenides could also be used. Ideallywith further irradiation, the silver layer 22 will be completelydiffused into the silver doped chalcogenide glass layer 20 d leaving noundoped remaining GeSe glass and forming a silver doped chalcogenideglass layer 20 d having regions of silver-selenide 20 e formed thereinas shown in FIG. 8C.

[0046] Referring now to FIG. 9, alternatively silver from layer 22 maybe incorporated into the glass layer 20 by light irradiation asdescribed above in combination with the thermal treatment describedabove. Preferably thermal treating would be done first to saturate aportion of the glass layer 20 with silver to form a silver containinggermanium-selenide glass layer 20 a wherein silver is incorporatedinterstitially. Then the substrate would be irradiated to form regionsof silver-selenide 20 e within the glass layer having silverincorporated interstitially therein 20 a. However, although it ispreferred that the silver be driven into the glass by thermal processingfirst then light irradiation, it is to be understood that the processmay be reversed, in that silver may be driven into the glass by lightirradiation first then thermal processing can be applied. Alternatively,light irradiation and thermal processing may be performedsimultaneously. Combining a light irradiation process with a thermalprocess to process silver into the glass layer provides aninterstitially formed silver containing glass layer 20 a havingsilver-selenide regions 20 e formed therein. Any remaining silver fromlayer 22 is then removed, for example, using wet etching in nitric acid.The preferred stoichiometric range for a combination of lightirradiation and thermal processing is between about Ge₁₈Se₈₂ to aboutGe₃₃Se₆₇ and is more preferably about Ge₂₅Se₇₅.

[0047] Referring now to FIG. 10, a second conductive electrode material24 is formed over the resulting silver containing chalcogenide glasslayer 20 a (FIG. 7) or 20 d/20 e (FIG. 8C) or 20 a/20 e (FIG. 9). Forexample, if a thermal treatment is used, the second conductive electrode24 is formed over the resulting interstially formed silver containingchalcogenide glass layer 20 a, if light irradiation is used, the secondconductive electrode 24 is formed over the silver doped chalcogenideglass layer 20 d having silver-selenide regions 20 e formed therein, orif a combination of thermal treatment and light irradiation is used, thesecond conductive electrode 24 is formed over the resultinginterstitially formed silver containing glass layer 20 a havingsilver-selenide regions 20 e formed therein. The second conductiveelectrode material 22 may comprise any electrically conductive material,for example, tungsten, tantalum or titanium, among many others, but doesnot contain silver.

[0048] Referring now to FIG. 11, one or more additional dielectriclayers 30 may be formed over the second electrode 24 and the firstdielectric layer 15 to isolate the resistance variable memory element100 from other structure fabrication over the substrate 10. Conventionalprocessing steps can then be carried out to electrically couple thefirst and second electrodes 14, 24 to various circuits of memory arrays.

[0049] Devices fabricated in accordance with the invention, limit theamount of silver available to migrate into the first chalcogenide glasslayer 17 by removing any remaining silver layer 22 and by using a secondelectrode that does not contain silver.

[0050] The resistance variable memory element 100 of the invention maybe used in a random access memory device. FIG. 12 illustrates anexemplary processing system 900 which utilizes a resistance variablememory random access device 101 containing an array of resistancevariable memory elements constructed as described above with referenceto FIGS. 1-11. The processing system 900 includes one or more processors901 coupled to a local bus 904. A memory controller 902 and a primarybus bridge 903 are also coupled the local bus 904. The processing system900 may include multiple memory controllers 902 and/or multiple primarybus bridges 903. The memory controller 902 and the primary bus bridge903 may be integrated as a single device 906.

[0051] The memory controller 902 is also coupled to one or more memorybuses 907. Each memory bus accepts memory components 908, which includeat least one memory device 101 of the invention. Alternatively, in asimplified system, the memory controller 902 may be omitted and thememory components directly coupled to one or more processors 901. Thememory components 908 may be a memory card or a memory module. Thememory components 908 may include one or more additional devices 909.For example, the additional device 909 might be a configuration memory.The memory controller 902 may also be coupled to a cache memory 905. Thecache memory 905 may be the only cache memory in the processing system.Alternatively, other devices, for example, processors 901 may alsoinclude cache memories, which may form a cache hierarchy with cachememory 905. If the processing system 900 include peripherals orcontrollers which are bus masters or which support direct memory access(DMA), the memory controller 902 may implement a cache coherencyprotocol. If the memory controller 902 is coupled to a plurality ofmemory buses 907, each memory bus 907 may be operated in parallel, ordifferent address ranges may be mapped to different memory buses 907.

[0052] The primary bus bridge 903 is coupled to at least one peripheralbus 910. Various devices, such as peripherals or additional bus bridgesmay be coupled to the peripheral bus 910. These devices may include astorage controller 911, an miscellaneous I/O device 914, a secondary busbridge 915, a multimedia processor 918, and an legacy device interface920. The primary bus bridge 903 may also coupled to one or more specialpurpose high speed ports 922. In a personal computer, for example, thespecial purpose port might be the Accelerated Graphics Port (AGP), usedto couple a high performance video card to the processing system 900.

[0053] The storage controller 911 couples one or more storage devices913, via a storage bus 912, to the peripheral bus 910. For example, thestorage controller 911 may be a SCSI controller and storage devices 913may be SCSI discs. The I/O device 914 may be any sort of peripheral. Forexample, the I/O device 914 may be an local area network interface, suchas an Ethernet card. The secondary bus bridge may be used to interfaceadditional devices via another bus to the processing system. Forexample, the secondary bus bridge may be an universal serial port (USB)controller used to couple USB devices 917 via to the processing system900. The multimedia processor 918 may be a sound card, a video capturecard, or any other type of media interface, which may also be coupled toone additional devices such as speakers 919. The legacy device interface920 is used to couple legacy devices, for example, older styledkeyboards and mice, to the processing system 900.

[0054] The processing system 900 illustrated in FIG. 12 is only anexemplary processing system with which the invention may be used. WhileFIG. 12 illustrates a processing architecture especially suitable for ageneral purpose computer, such as a personal computer or a workstation,it should be recognized that well known modifications can be made toconfigure the processing system 900 to become more suitable for use in avariety of applications. For example, many electronic devices whichrequire processing may be implemented using a simpler architecture whichrelies on a CPU 901 coupled to memory components 908 and/or memoryelements 100. These electronic devices may include, but are not limitedto audio/video processors and recorders, gaming consoles, digitaltelevision sets, wired or wireless telephones, navigation devices(including system based on the global positioning system (GPS) and/orinertial navigation), and digital cameras and/or recorders. Themodifications may include, for example, elimination of unnecessarycomponents, addition of specialized devices or circuits, and/orintegration of a plurality of devices.

[0055] The invention is not limited to the details of the illustratedembodiment. Accordingly, the above description and drawings are only tobe considered illustrative of exemplary embodiments which achieve thefeatures and advantages of the invention. Modifications andsubstitutions to specific process conditions and structures can be madewithout departing from the spirit and scope of the invention.Accordingly, the invention is not to be considered as being limited bythe foregoing description and drawings, but is only limited by the scopeof the appended claims.

1-53. (Cancelled).
 54. A resistance variable memory element comprising:a first chalcogenide glass layer; a first metal-chalcogenide layeroverlying and in electrical communication with said first chalcogenideglass layer, said first metal-chalcogenide layer represented by M_(x)C,wherein M is a metal, C is a chalcogenide chemical element, and x isabout 2; and a metal containing chalcogenide glass layer overlying andin electrical communication with said first metal-chalcogenide layer.55. The element of claim 54 wherein said metal containing chalcogenideglass layer has metal incorporated interstitially therein.
 56. Theelement of claim 54 wherein said metal containing chalcogenide glasslayer comprises silver-selenide formed in a chalcogenide glass layerhaving silver incorporated interstitially therein.
 57. The element ofclaim 56 wherein said metal containing chalcogenide glass layercomprises a material having the formula Ge_(x)Se_(100−x), wherein x isbetween about 18 to about
 43. 58. The element of claim 57 wherein saidmetal containing chalcogenide glass layer has a stoichiometry of aboutGe₄₀Se₆₀.
 59. The element of claim 54 wherein said metal containingchalcogenide glass layer comprises a metal doped chalcogenide glasslayer having silver-selenide incorporated therein.
 60. The element ofclaim 59 wherein said metal containing chalcogenide glass layercomprises a material having the formula Ge_(x)Se_(100−x), wherein x isbetween about 18 to about
 33. 61. The element of claim 60 wherein saidmetal containing chalcogenide glass layer has a stoichiometry of aboutGe₂₅Se₇₅.
 62. The element of claim 54 wherein said metal comprisessilver.
 63. The element of claim 54 wherein said first chalcogenideglass layer comprises a material having the formula Ge_(x)Se_(100−x),wherein x is between about 18 to about
 43. 64. The element of claim 63wherein said first chalcogenide glass layer has a stoichiometry of aboutGe₄₀Se₆₀.
 65. The element of claim 54 wherein said firstmetal-chalcogenide layer comprises silver-selenide.
 66. The element ofclaim 54 wherein said first chalcogenide glass layer has a thickness offrom about 100 Å to about 400 Å.
 67. The element of claim 54 whereinsaid first metal-chalcogenide layer has a thickness from about 300 Å toabout 600 Å.
 68. The element of claim 54 wherein said secondchalcogenide glass layer has a thickness of from about 150 Å to about500 Å.
 69. The element of claim 54 wherein said metal containingchalcogenide glass layer comprises metal-selenide.
 70. The element ofclaim 69 wherein said metal containing chalcogenide glass layercomprises silver-selenide.
 71. The element of claim 54 wherein saidmetal containing chalcogenide glass layer comprisesmetal-germanium-selenide.
 72. The element of claim 71 wherein said metalcontaining chalcogenide glass layer comprises silver-germanium-selenide.73. A resistance variable memory element comprising: a first electrode;a first germanium-selenide glass layer overlying and in electricalcommunication with said first electrode; a first silver-selenide layeroverlying and in electrical communication with said firstgermanium-selenide glass layer; a silver containing chalcogenide glasslayer overlying and in electrical communication with said firstsilver-selenide layer; and a second electrode overlying and inelectrical communication with said silver containing chalcogenide glasslayer.
 74. The element of claim 73 wherein said second electrode doesnot comprise silver.
 75. The element of claim 73 wherein said silvercontaining chalcogenide glass layer comprises a chalcogenide glass layerhaving silver formed interstitially therein.
 76. The element of claim 75wherein said silver containing chalcogenide glass layer comprises agermanium-selenide glass layer having silver formed interstitiallytherein.
 77. The element of claim 73 wherein said silver containingchalcogenide glass layer comprises silver-selenide formed in achalcogenide glass layer having silver formed interstitially therein.78. The element of claim 76 wherein said silver containing chalcogenideglass layer comprises silver-selenide formed in a germanium-selenideglass layer having silver formed interstitially therein.
 79. The elementof claim 73 wherein said silver containing chalcogenide glass layercomprises a silver doped chalcogenide glass layer having silver-selenideincorporated therein.
 80. The element of claim 78 wherein said silvercontaining chalcogenide glass layer comprises a silver dopedgermanium-selenide glass layer having silver-selenide incorporatedtherein.
 81. The element of claim 73 wherein said firstgermanium-selenide glass layer has a stoichiometry of between aboutGe₁₈Se₈₂ to about Ge₄₃Se₅₇.
 82. The element of claim 81 wherein saidfirst germanium-selenide glass layer has a stoichiometry of aboutGe₄₀Se₆₀.
 83. The element of claim 73 wherein said firstgermanium-selenide glass layer has a thickness of from about 100 Å toabout 400 Å.
 84. The element of claim 83 wherein said firstgermanium-selenide glass layer has a thickness of from about 150 Å toabout 200 Å.
 85. The element of claim 73 wherein said firstsilver-selenide layer has a thickness of from about 300 Å to about 600Å.
 86. The element of claim 78 wherein said second germanium-selenideglass layer has a stoichiometry of between about Ge₁₈Se₈₂ to aboutGe₄₃Se₅₇.
 87. The element of claim 86 wherein second germanium-selenideglass layer has a stoichiometry of about Ge₄₀Se₆₀.
 88. The element ofclaim 63 wherein said second germanium-selenide glass layer has athickness of from about 150 Å to about 500 Å.
 89. The element of claim78 wherein said second germanium-selenide glass layer has a thicknessabout 200 Å.
 90. The element of claim 80 wherein said silver containingchalcogenide glass layer has a germanium-selenide stoichiometry of aboutGe₁₈Se₈₂ to about Ge₃₃Se₆₇.
 91. The element of claim 90 wherein saidsilver containing chalcogenide glass layer has a stoichiometry of aboutGe₂₅Se₇₅.
 92. A processor-based system, comprising: a processor; and amemory circuit connected to said processor, said memory circuitincluding a resistance variable memory element comprising: a firstchalcogenide glass layer; a first metal-chalcogenide layer overlying andin electrical communication with said first chalcogenide glass layersaid first metal-chalcogenide layer represented by M_(x)C, wherein M isa metal, C is a chalcogenide chemical element, and x is about 2; and ametal containing chalcogenide glass layer overlying and in electricalcommunication with said first metal-chalcogenide layer.
 93. The systemof claim 92 wherein said metal containing chalcogenide glass layer hasmetal incorporated interstitially therein.
 94. The system of claim 92wherein said metal containing chalcogenide glass layer comprisessilver-selenide layer formed in a germanium-selenide layer having silverincorporated interstitially therein.
 95. The system of claim 92 whereinsaid metal containing chalcogenide glass layer comprises a silver dopedgermanium-selenide layer having silver-selenide incorporated therein.96. The system of claim 92 wherein said metal comprises silver.
 97. Thesystem of claim 92 wherein said first chalcogenide glass layer comprisesa material having the formula Ge_(x)Se_(100−x), wherein x is betweenabout 18 to about
 43. 98. The system of claim 97 wherein said firstchalcogenide glass layer has a stoichiometry of about Ge₄₀Se₆₀.
 99. Thesystem of claim 92 wherein said first metal-chalcogenide layer comprisessilver-selenide.
 100. The system of claim 92 wherein said firstchalcogenide glass layer has a thickness of from about 100 Å to about400 Å.
 101. The system of claim 92 wherein said first metal-chalcogenidelayer has a thickness from about 300 Å to about 600 Å.
 102. The systemof claim 92 wherein said second chalcogenide glass layer has a thicknessof from about 150 Å to about 500 Å.
 103. The system of claim 92 whereinsaid metal containing chalcogenide glass layer comprises metal-selenide.104. The system of claim 103 wherein said metal containing chalcogenideglass layer comprises silver-selenide.
 105. The system of claim 92wherein said metal containing chalcogenide glass layer comprises ametal-germanium-selenide layer.
 106. The system of claim 105 whereinsaid metal containing chalcogenide glass layer comprises asilver-germanium-selenide layer.
 107. The system of claim 92 whereinsaid metal containing chalcogenide glass layer comprises a materialhaving the formula Ge_(x)Se_(100−x), wherein x is between about 18 toabout
 33. 108. The system of claim 107 wherein said metal containingchalcogenide glass layer has a stoichiometry of about Ge₂₅Se₇₅.
 109. Thesystem of claim 92 wherein said metal containing chalcogenide glasslayer comprises a material having the formula Ge_(x)Se_(100−x), whereinx is between about 18 to about
 43. 110. The system of claim 109 whereinsaid metal containing chalcogenide glass layer has a stoichiometry ofabout Ge₄₀Se₆₀.